Here are some other simple digital devices you can build
with ReTrO. I suggest you build each of these and experiment with their
behaviors. You can also download each of these models. To download the
file, right-click on download .toy file and then click the 'Save
Target as' option. When you save, make sure to save with a .toy extension.
Data Latch - Essentially
an RS flip-flop with a modification made to the S and R inputs to avoid
the ambiguous state where R=1 and S=1.
D Flip-Flop - the
delay (D) flip-flop is a refinement of the data latch, incorporating
a second RS flip-flop. The data latch is enabled when the clock signal
goes Low, but the following flip-flop is enabled when the clock
goes High. Therefore, Q1 follows D whenever CK
is Low, but any change in the output of the combination Q
= Q2 is delayed until the next upward transition of CK. This
is an edge-triggered flip-flop, signified by the small triangle
on then function block.
JK Flip-Flop - This
widely used memory element provides three different modes of response.
Because of the feedback connections from output to input, the output
of a JK flip-flop depends on the states of the inputs and the outputs
at the instant the clock goes Low. With 0 inputs at J
and K, the clock has no effect and the flip-flop remains in its present
state Qo. With unequal inputs, the unit behaves like an RS flip-flop.
For J=1 and K=0, the clock Sets the flip-flop to
Q=1; for K=1 and J=0, the clock Resets the
flip-flop to Q=0. (With J not equal to K, Q
follows J.) With 1 inputs at both J and K,
the flip-flop toggles each time the clock goes Low. In its most
common form, the output changes states on the downward transitions of
the clock pulse. This is called a trailing-edge-triggered flip-flop.
4-bit Shift Register
- By using a series of JK flip-flops, one can build a serial
shift register. This device can store data by 'shifting' one bit
at a time from the input through the register. The data is entered beginning
with the least significant bit (LSB). One application for the register
is a serial-to-parallel converter, changing serial data to a
form that can be processed in parallel.
Multiplexer / Data Selector
- A multiplexer has many input lines and one output line. The output
is determined by manipulating the value on the Select input.
The binary value that is placed on the Select inputs determines
the data line whos data is transferred to the output line.
Demultiplexer / Data Distributor
- A demultiplexer performs the reverse operation of the multiplexer.
By manipulating the Select inputs and enabling the circuit with
a Low value on E, the decoder places a 0 on the
Output line corresponding to the Select code. All other
lines remain High.
Half Adder / Full
Adder - A half adder is a circuit which can add two bits together.
The output is two signals, sum and carry. By combining two half adders,
the full adder is created. This circuit is able to add three binary
inputs, the two operands and a carry bit. An adder for n-bit
addends is obtained by cascading n full-adder elements and connecting
the carry output to the carry input of the next higher stage.
Arithmetic Logic Unit
- the ALU performs arithmetic and logical operations on binary data.
All ALU's contain a function generator with an Adder that will combine
the content of the Accumulator with a word on the internal data bus
and place the result back on the data bus. The ALU also contains hardware
that will efficiently perform incrementing, left or right bit shifts,
and logic operations. In addition to the function generator, an ALU
also has a register for storing the result of the operations. This register
is traditionally called an accumulator.
Control Unit - The main function
of the control unit are hold the instruction currently be interpreted.
This in turn creates control signals which determine the operation of
the ALU and the computation of the address of the next instruction.
A control unit must contain
- Instruction register (IR)
- Address register (A)
- Program counter (PC)
- Subroutine register (S)
To allow for conditional selection of instructions, a multiplexer
is required at the input for selecting either PC (no branch) or A (branch).
After each instruction fetch, the PC is incremented.
Pulse Generator / One-Hot
Circuit - The processing of instructions requires two steps
or phases, the fetch phase and the execution phase. The
fetch phase consists of next instruction being loaded from the store
and during the execution phase, the operation is performed. For a simple
CPU, each instruction consists of 3 bytes, but only one byte can be
read during one clock cycle. Therefore, the fetch phase must be subdivided
into three subcycles. This yields four subcycles total for each instruction
cycle. A state machine can be used to generate these phase signals.
Because only four phases occur, a one-hot state machine can be used.
Note: Many of the diagrams and circuit explinations
were taken from 'Circuits, Devices, and Systems - Fifth Edition' by
Smith and Dorf. For a more indepth discussion, consult the text.