Tutorials

  1. ALU design (lab)
  2. CPU design (lab)
  3. Assembly for MC68332 (lab)
  4. C programming:
    Servo control
    (lab)
  5. Sensors and LCD ouput (lab)
  6. DC motor control (lab)
  7. Position control of differential-drive (lab)
  8. PSD, electromagnet (lab)
  9. Camera interface (lab)
  10. Image processing (lab)
  11. Final project (lab)
  12. Review

Embedded Systems 620.220

Example CPU's

CPU 1 - A very basic CPU. It is composed of the four basic CPU elements, the ALU, the CU, the memory store and the clock which provides the phase control. Notice that there is no branching available for this CPU. Therefore, the program written in the ROM executes the same way each time. This CPU also lacks the ability to write data back to the memory store.

Op-code
Description
Mnemonic
0
pc = pc + 1 NOP
1

acc = NOT acc

pc = pc + 1

NOT
2

acc = acc AND constant

pc = pc + 1

AND constant
3

acc = acc OR constant

pc = pc + 1

OR constant
4

acc = acc + constant

pc = pc + 1

ADD constant
5

acc = constant

pc = pc + 1

LOAD constant
6
Nothing N/A
7
Nothing N/A

 

CPU 2 - This CPU is an extention of the basic CPU 1. Two important features are added to make this CPU a basic model of the von Neumann architecture. The first feature is the ability to write data back to the memory store using op-code 6. The second feature is the conditional branch by selecting op-code 7.

Op-code
Description
Mnemonic
0
pc = pc + 2 NOP
1

acc = NOT acc

pc = pc + 2

NOT
2

acc = acc AND memory

pc = pc + 2

AND memory
3

acc = acc OR memory

pc = pc + 2

OR memory
4

acc = acc + memory

pc = pc +2

ADD memory
5

acc = memory

pc = pc +2

LOAD memory
6

memory = acc

pc = pc + 2

STORE acc
7

< acc unchanged >

if acc = 0 then pc = pc + address

else pc = pc + 2

BEQ address

 

CPU 3 - This CPU adds even more functionality. With this CPU, operations can be performed on either values at memory locations or directly on the values stored in the address register. This CPU also includes an unconditionaly break to an address.

Op-code
Description
Mnemonic
0

acc = constant

pc = pc + 2

LOAD constant
1

acc = memory

pc = pc + 2

LOAD memory
2

memory = acc

pc = pc + 2

STORE memory
3

acc = acc + memory

pc = pc +2

ADD memory
4

acc = acc AND memory

pc = pc + 2

AND memory
5

< acc unchanged >

if acc = 0 then pc = pc + address

else pc = pc + 2

BEQ address
6

< acc unchanged >

pc = pc + address

BRA address
7

acc = NOT acc

pc = pc + 2

NOT

 

CPU 4 - A complicated CPU which can perform operations on memory or constants. Notice that the interesting feature of this CPU is that the same set of operations can be performed with a value from a memory location or a constant stored in the address register.

Op-code
Description
Mnemonic
0

acc = memory

pc = pc + 2

LOAD memory
1

memory = acc

pc = pc + 2

STORE memory
2

acc = NOT acc

pc = pc + 2

NOT
3

acc = acc + memory

pc = pc + 2

ADD memory
4

acc = acc - memory

pc = pc + 2

SUB memory
5

acc = acc AND memory

pc = pc + 2

AND memory
6

acc = acc OR memory

pc = pc + 2

OR memory
7

< acc unchanged >

if acc = 0 then pc = pc + address

else pc = pc + 2

BEQ address
8

acc = constant

pc = pc + 2

LOAD constant
9
N/A N/A
10
N/A N/A
11

acc = acc + constant

pc = pc + 2

ADD constant
12

acc = acc - constant

pc = pc + 2

SUB constant
13

acc = acc AND constant

pc = pc +2

AND constant
14

acc = acc OR constant

pc = pc +2

OR constant
15

< acc unchanged >

pc = pc + address

BRA address

 

CPU 4 Timing Cycle - The timing cycle that the pulse generator and clock generate.

 

CPU Introduction  

Questions? Email Josh Petitt

last updated April 13, 2005 - © University of Western Australia